The useful question is what changes for users, developers or buyers, and whether the announcement stays industry context or becomes something people can actually use.

NVIDIA is collaborating with Cadence and Synopsys to optimize electronic design automation (EDA) applications for its Vera CPU, deploying it across workflows for upcoming processors. The move aims to address the growing complexity of chip design, where simulation, verification, and implementation stages rely heavily on CPU performance. Vera combines 88 custom NVIDIA Olympus CPU cores with LPDDR5X memory and a Scalable Coherent Fabric to deliver high per-core performance and low latency, particularly for latency-sensitive and large-scale regression workloads. The deployment reflects NVIDIA’s strategy to pair GPUs and AI with high-performance CPUs to improve overall design cycle efficiency.

Early testing on production-class workflows with Cadence Jasper and Synopsys VCS demonstrated up to 1.5x higher performance on selected workloads. Jasper uses smart proof technology and machine learning for early bug detection, while VCS simulates and validates complex chip designs before fabrication. Both applications showed performance gains when running on Vera, with the same core count as in the tests. NVIDIA is now working with both companies to profile applications, optimize software, and tune systems to broaden productivity improvements across more workflows over time.

Vera’s architecture includes 88 custom NVIDIA Olympus CPU cores, a high-efficiency LPDDR5X memory subsystem, and a second-generation NVIDIA Scalable Coherent Fabric. These components are designed to deliver strong per-core performance, high memory bandwidth, and consistent low latency, which are critical for demanding engineering workloads. The CPU’s capabilities are particularly beneficial for workloads that combine latency-sensitive tasks with large-scale regression testing across compute farms, enabling faster execution and greater throughput in verification processes.

The integration of Vera into NVIDIA’s EDA workflows underscores a broader strategy to accelerate chip design by leveraging the most suitable compute architecture for each task. While GPUs and AI accelerate many algorithms, high-performance CPUs remain essential for simulation, verification, and implementation workloads. NVIDIA plans to build on Vera with the next-generation Rosa CPU, powered by the NVIDIA Rigel core, continuing to optimize leading EDA applications across its CPU roadmap to create a feedback loop between silicon design, software optimization, and systems engineering.