d-Matrix Adopts NVIDIA NVLink Fusion for Rack-Scale XPU Deployment

d-Matrix, a developer of AI inference chips, announced it will adopt NVIDIA NVLink Fusion to connect its next-generation Raptor XPUs to NVIDIA’s AI infrastructure platform. The move integrates Raptor XPUs with NVIDIA’s scale-up and scale-out networking, MGX rack architecture, and broader AI platform, providing a faster path to deployment. According to Sid Sheth, d-Matrix cofounder and CEO, the collaboration addresses rising demand for inference while managing constraints in capital, time, and energy.

NVIDIA’s AI platform is described as vertically integrated and horizontally open, with NVLink Fusion extending this openness to third-party XPUs and CPUs. The technology enables silicon innovators to focus on processor design while leveraging NVIDIA’s infrastructure for deployment at AI factory scale. NVLink Fusion provides interconnects, rack architecture, software, and supply chain integration, reducing the complexity of building custom infrastructure from scratch.

The adoption of NVLink Fusion offers d-Matrix a 3x lower XPU-to-XPU latency than Ethernet, 10x higher packet rates, and 3 TB/s per XPU of all-to-all bandwidth via sixth-generation NVLink. By integrating with NVIDIA’s MGX ecosystem, d-Matrix gains access to validated rack designs, power and cooling infrastructure, and a mature supply chain. This standardization allows data centers to support GPUs, CPUs, and XPUs within a single rack architecture.

d-Matrix plans to connect its XPUs in a high-bandwidth, low-latency scale-up domain and integrate additional NVIDIA components, including Vera CPUs, ConnectX-9 SuperNICs, BlueField-4 DPUs, and Spectrum-X networking. The collaboration positions d-Matrix to deploy specialized inference alongside NVIDIA systems within unified AI factories, leveraging NVIDIA’s full-stack platform for performance and efficiency.