OFICIAL Intel Newsroom

Intel’s U.S. Advanced Packaging Enables Next-Generation AI Semiconductors

What happened
Based on Intel Newsroom · Jul 29, 2026

Intel expands U.S. advanced packaging capabilities at its Rio Rancho, New Mexico facility, scaling multi-chip systems to 8x the industry standard and over 12x by 2028 to meet AI workload demands.

Video

Video available

Key points
·
Top View of Computer Chip on Conveyor Line during Production and Packaging Process on Semiconductor Fab.
·
Advanced packaging is the essential craft of interconnecting multiple specialized chips together.
·
This allows them to function as a single, powerful unit that runs faster handling the massive workloads of the future.
·
Intel’s been doing advanced chip packaging for years in the U.S.
Key numbers
·
The facility now scales multi-chip packages to 8x the current industry standard, with plans to exceed 12x by 2028.
·
advanced packaging capabilities at its Rio Rancho, New Mexico facility, scaling multi-chip systems to 8x the industry standard and over 12x by 2028 to meet AI workload demands.

Intel’s Rio Rancho, New Mexico site has transitioned from 6-inch wafer production in the 1980s to leading U.S. advanced packaging, employing 2,700 workers and 500 suppliers. The facility now scales multi-chip packages to 8x the current industry standard, with plans to exceed 12x by 2028. Advanced packaging connects specialized chiplets into a single system, enabling faster performance for AI workloads. Katie Prouty, manager of Fab 9, notes the site’s historical shift and its role in meeting modern semiconductor demands.

Intel Foundry uses Foveros stacking to interconnect chiplets on a silicon interposer, likened to a pizza crust, where smaller specialized tiles are attached and baked into a unified package. The process begins with a chip attach tool that places chiplets on the interposer, followed by baking, epoxy filling, and precision dicing. Foveros enables combining chips from different designs or technology nodes into one wafer, improving efficiency and reducing power consumption in devices like laptops and edge computing systems.

EMIB (Embedded Multi-die Interconnect Bridge) technology links specialized chips on a package using tiny silicon bridges embedded in the substrate, allowing different chips to function as a single unit. This approach enhances AI performance while lowering costs by avoiding large silicon interposers. Intel embeds high-speed bridges only where needed, creating a cost-effective ‘silicon mosaic’ of chiplets that improves data center efficiency and reduces manufacturing expenses.

Intel Foundry’s latest development, EMIB-T, introduces power delivery channels through the bridge to directly supply chips, improving power efficiency and signal routing for high-bandwidth memory technologies. The company’s ability to mix chiplets from various sources onto large substrates supports next-generation AI engines for data centers. A collaboration with Lens Technology aims to enhance AI and data center performance, while investments in Ireland are expected to create high-tech jobs and expand manufacturing capacity.

Original source → Deals on Clipraptor.com →